Modeling and Thermal Stress Coupling Optimization Design of TSV Inductors in On-Chip DC/DC Converters

• Published in: IEEE access Vol. 11; pp. 133189 - 133198
• Main Authors: Wang, Huangyin, Xiong, Yikai, Geng, Liming
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Deep learning; deep reinforcement learning; Design optimization; Direct current; Electric converters; Inductance; inductance model; Inductors; Integrated circuits; Interconnections; Magnetic cores; Model accuracy; Modelling; Parasitics (electronics); Reinforcement learning; Resistance factors; Silicon; Stress; Thermal stress; thermal stress coupling; Thermal stresses; Through-silicon vias; TSV inductor; Voltage converters (DC to DC)
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2023.3336705

As advances in fabrication technology continue and the power density of microelectronic devices increases, efficient and highly integrated through-silicon via (TSV) inductors have emerged as a viable solution for addressing challenges in power and thermal stress management in on-chip direct current-to-direct current (DC/DC) converters. This study proposes a method for modeling and optimizing TSV inductors with magnetic cores based on thermal stress and lumped circuit. CoZrTa is selected as the magnetic core material, and RLCG circuit modeling is performed for multiple factors, including resistance, inductance value, and parasitic capacitance. To validate the accuracy of the model, simulation tests were conducted using ANSYS HFSS and SPICE tools. The results show that under low-frequency conditions (< 2GHz), the error between the model and the 3D full-wave simulation for <inline-formula> <tex-math notation="LaTeX">L </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">{Q} </tex-math></inline-formula> parameters is less than 3.3%, proving the model's accuracy. Furthermore, a deep reinforcement learning optimization design model based on the deep deterministic policy gradients (DDPG) algorithm is proposed, which comprehensively considers factors such as current ripple, power loss, parasitic parameters, and thermal stress. With almost no change in electrical performance, the thermal stress in the optimized TSV inductor array decreased by 11.91% and its distribution was improved, reducing the likelihood of fatigue damage.