Macro Memory Cell Generator for SKY130 PDK

• Published in: IEEE access Vol. 12; pp. 59688 - 59701
• Main Authors: Baungarten-Leon, Emilio Isaac, Ortega-Cisneros, Susana, Pinedo-Diaz, German, Rivera Acosta, Miguel Angel, Rodriguez Navarrete, Francisco Javier, Jaramillo-Toral, Uriel, Gonzlez, Cristian Torres, Lopez, Juan Carlos Garcia
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Arrays; Automation; Configurations; Data systems; Design; Designers; Floorplans; Framework; Industries; Interleaved codes; interleaving memory; Layout; memory design; Memory management; OpenLane; Random access memory; SKY130 PDK; SRAM; SRAM chips; Static random access memory; System performance; Very large scale integration; VLSI; Voltage
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2024.3393479

The SKY130 Process Design Kit (PDK) offers limited options for Static Random-Access Memory (SRAM) configurations, providing only three predefined memory sizes: <inline-formula> <tex-math notation="LaTeX">8\times 1024 </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">32\times 256 </tex-math></inline-formula>, and <inline-formula> <tex-math notation="LaTeX">32\times 512 </tex-math></inline-formula>, this poses a challenge for designers who require memories with different characteristics, as they must either design an entire memory architecture from scratch or resort to interleaving techniques with the available memory configurations. To address this issue, we present a novel framework that automates the generation of multiple memory arrays with custom floorplans, leveraging the concept of interleaving memory. Our framework enables designers to create various sizes and configurations memories by combining and interleaving the existing SKY130 PDK memories, additionally, the framework allows designers to easily specify their desired memory size, word length, floorplan, and other essential parameters. The framework then automatically generates multiple memory arrays that meet the specified requirements. Furthermore, it provides the files required by OpenLane, facilitating the seamless integration of these memories into the Register Transfer Level (RTL) to Graphic Data System II (GDSII) flow. The key advantage of our framework lies in its ability to streamline the creation of custom memories by automating the interleaving process and offering flexibility in floorplan design. This significantly reduces design time and effort, empowering designers to efficiently create memories with specific characteristics while adhering to the limitations of the SKY130 PDK. The framework thus serves as a valuable tool for memory design in the context of the SKY130 PDK, opening doors for more efficient and optimized chip designs.