An Efficient Massive MIMO Detector Based on Second-Order Richardson Iteration: From Algorithm to Flexible Architecture

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 67; no. 11; pp. 4015 - 4028
• Main Authors: Tu, Jiaming, Lou, Mengdan, Jiang, Jianfei, Shu, Dewu, He, Guanghui
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Approximation algorithms; CMOS; Complexity; Complexity theory; Computer architecture; Convergence; Correlation; Detectors; Energy conversion efficiency; Error detection; Hardware; Iterative methods; Likelihood ratio; Massive MIMO; MIMO (control systems); MIMO communication; MMSE; second-order Richardson iteration; signal detection; VLSI
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2020.3010890

Aiming at reducing the complexity of minimum mean square error (MMSE) detection in massive multiple-input multiple-output (MIMO) systems, this paper proposes a detection algorithm with high convergence rate and an efficient hardware architecture based on second-order Richardson iteration (SORI). In the proposed algorithm, a pre-iteration-based initialization method is presented to accelerate the convergence without extra complexity. In addition, the approximation of relaxation factor and the log-likelihood ratio (LLR) is introduced to further reduce computing load. Theoretical analysis demonstrates the advantages of the proposed algorithm in fast convergence and low complexity, and simulation results show that the proposed algorithm can efficiently approach MMSE performance. Based on this algorithm, a flexible hardware architecture is designed, which is deeply pipelined to support <inline-formula> <tex-math notation="LaTeX">128\times U </tex-math></inline-formula> (<inline-formula> <tex-math notation="LaTeX">8\leq U\leq 32 </tex-math></inline-formula>) massive MIMO detection with the configurable number of iterations, and a folded dual-mode systolic array (DMSA) is fully utilized to achieve the flexibility with low hardware consumption. Implemented on Xilinx Virtex-7 FPGA and SMIC 40nm CMOS technology, the proposed detector is competitive in terms of energy and area efficiency compared to state-of-the-art iterative detectors, and it can adapt to the varied channel condition and the number of users in massive MIMO systems.