Modeling Multiple-Input Switching in Timing Analysis Using Machine Learning

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 40; no. 4; pp. 723 - 734
• Main Authors: Shashank Ram, O. V. S., Saurabh, Sneh
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analytical models; Artificial neural networks; Circuit analysis; CMOS integrated circuits; Computation; Computational modeling; Delay; Delays; electronic design automation and methodology; Gates (circuits); Integrated circuit modeling; Learning theory; Load modeling; Logic gates; Machine learning; Methodology; Polynomials; Regression analysis; Support vector machines; Switches; Switching; timing
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2020.3009624

Traditional timing analysis employs a delay model that assumes only a single input switches for a gate during a transition, while all side inputs are held constant to noncontrolling values. However, ignoring the impact of multiple-input switching (MIS) can lead to either an overestimation or an underestimation of a gate delay. In this article, we examine the impact of MIS in the delay of different types of gates under varying conditions of load, slew, and temporal distance of signals at the inputs. We model the impact of MIS by deriving a corrective measure that should be applied to the conventional single-input switching (SIS) delay under different conditions. We call this corrective measure as MIS-SIS difference (MSD). In this work, we have evaluated polynomial regressions, support vector regression, and artificial neural networks (ANNs) to model MSD. Additionally, we integrate the ANN-based MSD model into existing timing libraries and employ them in carrying out MIS-aware timing analysis. We test the proposed methodology on some benchmark circuits and demonstrate that the proposed technique can improve the accuracy of timing analysis effectively. For example, for ISCAS'85 C17 circuit having short paths, under the MIS scenario, traditional SIS-based delay differs from the corresponding SPICE-computed delay by as large as 120%. However, the delay computed using the proposed methodology under the MIS scenario for the same circuit differs from the SPICE-computed delay by less than 3%. Additionally, the runtime overhead of the proposed methodology during timing analysis is negligible.