Analog Current-Mode 8-Point Approximate-DFT Multi-Beamformer With 4.7 Gbps Channel Capacity

• Published in: IEEE access Vol. 11; pp. 53716 - 53735
• Main Authors: Zhao, Haixiang, Madanayake, Arjuna, Cintra, Renato J., Mandal, Soumyajit
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Analog beamforming; analog computing; Antenna arrays; Array signal processing; Beamforming; Channel capacity; Circuits; Computer architecture; Current mirrors; current-mode circuit; Current-mode circuits; Discrete Fourier transforms; dynamic current mirror; Fourier transforms; Linear transformations; multi-beamformer; Power consumption; Power management; Transistors; Wireless networks
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2023.3279722

This paper describes a current-mode on-chip analog architecture suitable for multi-beamforming of IF band signals from small- to moderate-sized antenna arrays. The architecture uses an approximate discrete Fourier transform (a-DFT) to realize the linear transformation (LT) required for multi-beamforming. Compared with the ideal DFT, the a-DFT algorithm exhibits good enough accuracy while only utilizing small integer coefficients, allowing it to be easily realized as a current-mode circuit. The 8-point a-DFT demonstrated in this paper can be used as the core calculation block in a standalone beamforming system and also serve as the key computational block in modularized multi-beamformer systems for larger arrays. The design uses an offset cancellation technique based on a multi-phase dynamic current mirror (DCM) to decrease errors in the generated beam pattern caused by transistor mismatches. The proposed integrated multi-beamformer was realized in the TSMC 180 nm process. Test results show that the chip can support 8-point multi-beamforming with 54 dB dynamic range (DR) and 4.7 Gbps channel capacity. The chip has approximately 40.8% lower power consumption than a fully-digital 8-point a-DFT core synthesized using the NCSU 45 nm PDK. When used within a complete beamforming system, the chip can also save system-level power consumed by the digital blocks, such as reducing ADC power consumption by 69.5% to 92.9% as estimated from the median Walden FoM of recent work.