Synthesizable Memory Arrays Based on Logic Gates for Subthreshold Operation in IoT

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 66; no. 3; pp. 941 - 954
• Main Authors: Xin Fan, Stuijt, Jan, Bo Liu, Gemmeke, Tobias
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Clocks; Design standards; Electric potential; IoT; Latches; Leakage; Logic arrays; Logic circuits; Logic gates; memories; Multiplexing; Random access memory; Standard cells; State of the art; Static random access memory; subthreshold; Synthesis; Voltage measurement
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2018.2873026

This paper identifies novel directions of standard-cell-based synthesizable memory design. A compact 18T-bitcell of OR-AND-Invert (OAI) and AND-OR-Invert (AOI) logic gates is presented with bit-selective write and multiplexed read accesses. It reduces the bitcell area by 11%-40% compared to the state-of-the-art clock-gating-based D-latch schemes while avoiding custom-cell design. The improved storage density comes from the tight integration on two levels-coupling the read multiplexing within each bitcell and taking advantage of structured datapath placement in bitcell arrays by using commercial CAD tools. As measured on a 40 nm SRAM of 90 kb, the OAI/AOI-gatebased synthesizable memory features 0.4 V minimum access voltage, 30 fJ minimum read energy per bit, and a leakage power of 1.4 pW per bit at 0.3 V data retention voltage. It is ideally suited for IoT-node design operating in sub-Vt for joint dynamic energy and leakage power reduction. Further, it enables fast turnaround times by IP reuse over technology nodes with minimal (re)design effort.