CMOS-based Single-Cycle In-Memory XOR/XNOR

• Published in: IEEE access Vol. 12; p. 1
• Main Authors: Alam, Shamiul, Hutchins, Jack, Shukla, Nikhil, Asifuzzaman, Kazi, Aziz, Ahmedullah
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01.01.2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Artificial intelligence; Artificial neural networks; Big Data; CMOS; Compute-in-Memory; Encryption; Image classification; Integrated circuit modeling; Logic gates; Network latency; Nonvolatile memory; Sensors; Topology; Transistors; Verification; Voltage; XNOR; XOR
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2024.3384752

Big data applications are on the rise, and so is the number of data centers. The ever-increasing massive data pool needs to be periodically backed up in a secure environment. Moreover, a massive amount of securely backed-up data is required for training binary convolutional neural networks for image classification. XOR and XNOR operations are essential for large-scale data copy verification, encryption, and classification algorithms. The disproportionate speed of existing compute and memory units makes the von Neumann architecture inefficient to perform these Boolean operations. Compute-in-memory (CiM) has proved to be an optimum approach for such bulk computations. The existing CiM-based XOR/XNOR techniques either require multiple cycles for computing or add to the complexity of the fabrication process. Here, we propose a CMOS-based hardware topology for single-cycle in-memory XOR/XNOR operations. Our design provides at least 2× improvement in the latency compared with other existing CMOS-compatible solutions. We verify the proposed system through circuit/system-level simulations and evaluate its robustness using a 5000-point Monte Carlo variation analysis. This all-CMOS design paves the way for practical implementation of CiM XOR/XNOR at scaled technology nodes.