A PWM Nie-Tan Type-Reducer Circuit for a Low-Power Interval Type-2 Fuzzy Controller

A novel Type-Reduction/Defuzzification circuit architecture for an analog interval type-2 fuzzy inference system is proposed. Based on the Nie-Tan type-reduction method, the circuit operates with current-mode inputs, representing the firing intervals of the rules created by the inference engine, and...

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Bibliographic Details
Published inIEEE access Vol. 9; pp. 158773 - 158783
Main Authors de Souza, Gabriel Antonio Fanelli, Santos, Rodrigo Bispo Dos, de Abreu Faria, Lester
Format Journal Article
LanguageEnglish
Published Piscataway IEEE 2021
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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Summary:A novel Type-Reduction/Defuzzification circuit architecture for an analog interval type-2 fuzzy inference system is proposed. Based on the Nie-Tan type-reduction method, the circuit operates with current-mode inputs, representing the firing intervals of the rules created by the inference engine, and generating a PWM output. It is demonstrated that by selecting an appropriate number of consequents it is possible to create the PWM output directly, without the need for analog multiplier/divider circuits. This feature makes the circuit very simple, aiding in the design process, while the PWM output makes it suitable for controlling DC-DC converters, maximum power point trackers (MPPT) for energy generators, or other switching applications. It is designed to achieve very low power consumption, allowing its use in power restrained environments, such as energy harvesting systems. The circuit was designed using TSMC <inline-formula> <tex-math notation="LaTeX">0.18~\mu \text{m} </tex-math></inline-formula> technology, in CADENCE Virtuoso software, and simulated for different combinations of input values, demonstrating its capabilities. It was also simulated as part of a type-2 fuzzy inference system with two inputs, nine rules, and firing intervals represented by currents within 0 and <inline-formula> <tex-math notation="LaTeX">10~\mu \text{A} </tex-math></inline-formula>. The circuit was prototyped, and the experimental average power consumption was only <inline-formula> <tex-math notation="LaTeX">53.8~\mu \text{W} </tex-math></inline-formula>, validating its low power consumption characteristic.
ISSN:2169-3536
2169-3536
DOI:10.1109/ACCESS.2021.3131877