Configurable sparse matrix - matrix multiplication accelerator on FPGA: A systematic design space exploration approach with quantization effects

High-performance sparse matrix multipliers are essential for deep learning applications, and as big data analytics continues to evolve, specialized accelerators are also needed to efficiently handle sparse matrix operations. This paper proposes a modified, configurable, outer product based architect...

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Bibliographic Details
Published inAlexandria engineering journal Vol. 91; pp. 84 - 94
Main Authors Noble, G., Nalesh, S., Kala, S., Kumar, Akash
Format Journal Article
LanguageEnglish
Published Elsevier B.V 01.03.2024
Elsevier
Subjects
Accelerator
FPGA
Outer product
Quantization
Sparse matrix multiplication
SpGEMM
Quantization
FPGA
Outer product
Sparse matrix multiplication
SpGEMM
Accelerator
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Summary:High-performance sparse matrix multipliers are essential for deep learning applications, and as big data analytics continues to evolve, specialized accelerators are also needed to efficiently handle sparse matrix operations. This paper proposes a modified, configurable, outer product based architecture for sparse matrix multiplication, and explores design space of the proposed architecture. The performance of various architecture configurations has been examined for input samples with similar characteristics. The proposed architecture has been implemented on Xilinx Kintex-7 FPGA using 32-bit single precision floating-point arithmetic and also in 8-bit, 16-bit and 32-bit fixed-point arithmetic formats. The effect of quantization in the proposed architecture has been analyzed extensively and the results have been reported. The performance of the proposed architecture has been compared with state-of-the-art implementations, and an improvement of 9.21% has been observed in the performance.
ISSN:1110-0168
DOI:10.1016/j.aej.2024.01.075