Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 21; no. 6; pp. 989 - 999
• Main Authors: Whatmough, P. N., Das, S., Bull, D. M., Darwazeh, I.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.06.2013; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adders; Applied sciences; Circuit properties; Circuits; Delay; Design. Technologies. Operation analysis. Testing; Digital circuits; Digital signal processing; Digital signal processors; Discrete cosine transform (DCT); dynamic voltage scaling (DVS); Electric potential; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Error analysis; Error correction; Error detection; Exact sciences and technology; finite-impulse response (FIR); Frequency filters; Integrated circuits; Integrated circuits by function (including memories and processors); process variation; razor; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Studies; Time measurements; Topology; Very large scale integration; Voltage; Voltage control; Discrete cosine transform (DCT); Error rate; Feedback regulation; Digital processing; Actuation voltage; Dynamic conditions; Fault tolerance; Flip-flop circuits; Feedback; Energetic efficiency; process variation; Robustness; Delay time; Voltage regulation; Power electronics; dynamic voltage scaling (DVS); Power filters; Control loop; finite-impulse response (FIR); Summing circuits; Integrated circuit; Carry logic; Signal processing; Critical path; razor; Error correction; Low-power electronics; Digital signal processor
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2012.2202930

In this paper, we present a novel circuit-level timing error mitigation technique, which aims to increase energy-efficiency of digital signal processing datapaths without loss of robustness. Timing errors are detected using razor flip-flops on critical-paths, and the error-rate feedback is used to control a dynamic voltage scaling control loop. In place of conventional razor error correction by replay, we propose a new approach to bound the magnitude of intermittent timing errors at the circuit level. A timing guard-band is created by shaping the path delay distribution such that the critical paths correspond to a group of least-significant bit registers. These end-points are ensured to be critical by modifying the topology of the final stage carry-merge adder, and by using tool-based device sizing. Hence, timing violations lead to weakly correlated logical errors of small magnitude in a mean-squared-error sense. We examine this approach in an finite-impulse response (FIR) filter and a 2-D discrete cosine transform implementation, in 32-nm CMOS. Power saving compared to a conventional design at iso-frequency is 21%-23% at the typical corner, while retaining a voltage guard-band to protect against fast transient changes in switching activity and supply noise. The impact on minimum clock period is small (16%-20%), as it does not necessitate the use of ripple-carry adders and also requires only a bare minimum of additional design effort.