Compact Modeling of Transition Metal Dichalcogenide based Thin body Transistors and Circuit Validation

• Published in: IEEE transactions on electron devices Vol. 64; no. 3; pp. 1261 - 1268
• Main Authors: Yadav, Chandan, Agarwal, Amit, Chauhan, Yogesh Singh
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2017; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 2-D semiconductor; Chalcogenides; circuit simulation; compact model; Computer simulation; Electric potential; Field effect transistors; Integrated circuit modeling; Logic gates; Mathematical model; Metals; Molybdenum disulfide; molybdenum disulphide (MoS₂); molybdenum ditelluride (MoTe₂); Semiconductor device modeling; Semiconductor devices; Transistors; transition metal dichalcogenide (TMD); tungsten diselenide (WSe₂); Two dimensional models
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2016.2643698

In this paper, we present a compact model for surface potential and drain current in transition metal dichalcogenide (TMD) channel material-based n-type and p-type FETs. The model considers 2-D density of states and Fermi-Dirac statistics along with drift-diffusion transport model and includes velocity saturation and trap state effects. The developed model has been implemented in Verilog-A and is applicable for symmetric double gate as well as top-gated TMD-on-insulator FETs. The presented model is extensively validated with simulation as well as experimental data for different TMD materials-based FETs and shows excellent agreement with both the simulation and the experimental data. We further validate the model at circuit level using experimental data of MoS 2 FET-based inverter.