A Quatro-Based 65-nm Flip-Flop Circuit for Soft-Error Resilience

A flip-flop circuit hardened against soft errors is presented in this paper. This design is an improved version of Quatro for further enhanced soft-error resilience by integrating the guard-gate technique. The proposed design, as well as reference Quatro and regular flip-flops, was implemented and m...

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Bibliographic Details
Published inIEEE transactions on nuclear science Vol. 64; no. 6; pp. 1554 - 1561
Main Authors Li, Y.-Q, Wang, H.-B, Liu, R., Chen, L., Nofal, I., Shi, S.-T, He, A.-L, Guo, G., Baeg, S. H., Wen, S.-J, Wong, R., Chen, M., Wu, Q.
Format Journal Article
LanguageEnglish
Published New York IEEE 01.06.2017
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Circuit design
Circuit faults
Circuits
CMOS
Design
Design improvements
Errors
Flip-Flop
Flip-flops
Hardening
Heavy ions
Ions
Quatro
Radiation hardening (electronics)
radiation hardness by design (RHBD)
Redundancy
Resilience
soft error
Soft errors
Transistors
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Summary:A flip-flop circuit hardened against soft errors is presented in this paper. This design is an improved version of Quatro for further enhanced soft-error resilience by integrating the guard-gate technique. The proposed design, as well as reference Quatro and regular flip-flops, was implemented and manufactured in a 65-nm CMOS bulk technology. Experimental characterization results of their alpha and heavy ions soft-error rates verified the superior hardening performance of the proposed design over the other two circuits.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2017.2704062