The flash memory read path: building blocks and critical aspects

The ever-increasing demand for portable equipment is leading to the use of flash memory devices for nonvolatile storage. Fast access time and low power consumption are obviously key requirements. Moreover, multilevel storage techniques are mandatory to reduce the cost per megabit. As a consequence,...

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Bibliographic Details
Published inProceedings of the IEEE Vol. 91; no. 4; pp. 537 - 553
Main Authors Micheloni, R., Crippa, L., Sangalli, M., Campardo, G.
Format Journal Article
LanguageEnglish
Published New York IEEE 01.04.2003
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Acceleration
Access time
Circuits
Cost engineering
Costs
Decoding
Devices
Electronic switching systems
Energy consumption
Flash memory
Flash memory (computers)
Marketing
Matrix converters
Multilevel
Power consumption
Timing
Voltage
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Summary:The ever-increasing demand for portable equipment is leading to the use of flash memory devices for nonvolatile storage. Fast access time and low power consumption are obviously key requirements. Moreover, multilevel storage techniques are mandatory to reduce the cost per megabit. As a consequence, the READ operation becomes more and more critical, and optimized solutions are needed for almost all circuits involved in the read path. This paper examines the whole read path from addresses to data output, and describes several schemes developed to achieve the required high performances.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
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ISSN:0018-9219
1558-2256
DOI:10.1109/JPROC.2003.811704