PVT Variation Tolerant Current Source With On-Chip Digital Self-Calibration

A current source with a small current error has been proposed to maintain the bandwidth of the system without an increase in power consumption for a margin. It minimizes the current error under process, supply voltage, and temperature (PVT) variations. Because the on-resistance of the nMOS array is...

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Bibliographic Details
Published inIEEE transactions on very large scale integration (VLSI) systems Vol. 20; no. 4; pp. 737 - 741
Main Authors Kim, Moo-Young, Lee, Hokyu, Kim, Chulwoo
Format Journal Article
LanguageEnglish
Published New York, NY IEEE 01.04.2012
Institute of Electrical and Electronics Engineers
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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