PVT Variation Tolerant Current Source With On-Chip Digital Self-Calibration

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 20; no. 4; pp. 737 - 741
• Main Authors: Kim, Moo-Young, Lee, Hokyu, Kim, Chulwoo
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.04.2012; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: All digital gates; and temperature (PVT) detector; Applied sciences; Arrays; Clocks; CMOS; current source; Current sources; Delay; Design. Technologies. Operation analysis. Testing; Detectors; Digital; Electric potential; Electrical engineering. Electrical power engineering; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Errors; Exact sciences and technology; General equipment and techniques; Instruments, apparatus, components and techniques common to several branches of physics and astronomy; Integrated circuits; MOS devices; on-chip; Physics; Power demand; Power electronics, power supplies; process; Resistors; self-calibration; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Sensors (chemical, optical, electrical, movement, gas, etc.); remote sensing; supply voltage; Very large scale integration; Voltage; Current source; process; and temperature (PVT) detector; Measurement sensor; self-calibration; Temperature sensor; Power supply; Power electronics; on-chip; All digital gates; Implementation; Selfcalibration; Complementary MOS technology; Electric power consumption; supply voltage; NMOS technology
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2011.2109971

A current source with a small current error has been proposed to maintain the bandwidth of the system without an increase in power consumption for a margin. It minimizes the current error under process, supply voltage, and temperature (PVT) variations. Because the on-resistance of the nMOS array is self-calibrated digitally by an on-chip digital PVT detector, a current error of only ±2% is achieved. The current source has been implemented in an 80-nm CMOS process, occupies 0.018 mm 2 and consumes 94.9 μW at a supply voltage of 1.0 V.