Performance and Variations Induced by Single Interface Trap of Nanowire FETs at 7-nm Node

• Published in: IEEE transactions on electron devices Vol. 64; no. 2; pp. 339 - 345
• Main Authors: Yoon, Jun-Sik, Kim, Kihyun, Rim, Taiuk, Baek, Chang-Ki
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.02.2017; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 7-nm node; <italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">RC delay; Air gaps; Delays; FinFETs; interface trap; Ions; Leakage current; Logic gates; nanowire (NW) FET; Nanowires; OFF-state current; Performance evaluation; variability
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2016.2633970

DC/AC performance and the variations due to single interface trap of the nanowire (NW) FETs were investigated in the 7-nm technology node using fully calibrated TCAD simulation. Shorter junction gradient and greater diameter reduced RC delay without short channel degradations. Spacer with smaller dielectric constants decreased parasitic and gate capacitances with a slight decrease of ON-state currents, thus minimizing RC delay. Interface traps for the variability analysis were P b0 , P b1 , and fixed oxide charges at the Si/SiO 2 interface. P b0 negligibly affected dc variations but P b1 at the drain underlap regions increased gate-induced drain leakage currents, which induced greater OFF-state current variations. Fixed oxide charges, especially at the middle of the channel regions, shifted drain currents toward left by bending the energy band downward locally near the single interface trap. To maximize the performance as well as to minimize the variations induced by the interface traps, careful surface treatment for the drain underlap regions and adaptation of vertical NW structure are needed while maintaining fine short channel characteristics.