Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 16; no. 7; pp. 830 - 836
• Main Authors: Carbognani, F., Buergin, F., Felber, N., Kaeslin, H., Fichtner, W.
• Format: Journal Article
• Language: English
• Published: Piscataway, NJ IEEE 01.07.2008; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Architecture; Arithmetic; Circuit properties; CMOS; CMOS technology; Design. Technologies. Operation analysis. Testing; Digital circuits; Dissipation; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Energy dissipation; Energy efficiency; Energy measurement; Exact sciences and technology; Filtering; glitch; Glitches; Integrated circuits; Integrated circuits by function (including memories and processors); low frequency; Low pass filters; low power; multiplier; Multipliers; Propagation delay; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors; Signal processing; Size measurement; switching activity; Technological innovation; Transistors; transmission gate; Transmission gates; Very large scale integration; switching activity; low frequency; Low voltage; Spurious signal; glitch; Energy dissipation; Energetic efficiency; Complementary MOS technology; Frequency converter; 16 bit Processor; Delay time; Arithmetic circuit; multiplier; Transistor; Voltage spike; Adder; Switching; Dimensioning; Frequency multiplier; Integrated circuit; Signal processing; Capacitance; low power; transmission gate; Low-power electronics; Arithmetic
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2008.2000457

Various 16-bit multiplier architectures are compared in terms of dissipated energy, propagation delay, energy-delay product (EDP), and area occupation, in view of low-power low-voltage signal processing for low-frequency applications. A novel practical approach has been set up to investigate and graphically represent the mechanisms of glitch generation and propagation. It is found that spurious activity is a major cause of energy dissipation in multipliers. Measurements point out that, because of its shorter full-adder chains, the Wallace multiplier dissipates less energy than other traditional array multipliers (8.2 mu W/MHz versus 9.6 mu W/MHz for 0.18mum CMOS technology at 0.75 V). The benefits of transistor sizing are also evaluated (Wallace including minimum-size transistors dissipates 6.2 muW/MHz). By combining transmission gates with static CMOS in a Wallace architecture, a new approach is proposed to improve the energy-efficiency further (4.7 muW/MHz), beyond recently published low-power architectures. The innovation consists in suppressing glitches via resistance-capacitance low-pass filtering, while preserving unaltered driving capabilities. The reduced number of V dd -to-ground paths also contributes to a significant decrease of static consumption.