Scheduling Back-End Operations in Semiconductor Manufacturing

• Published in: IEEE transactions on semiconductor manufacturing Vol. 23; no. 2; pp. 210 - 220
• Main Authors: Yumin Deng, Bard, Jonathan F, Chacon, G Rodolfo, Stuber, John
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2010; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Assembly; Circuit testing; Cycle time; Dispatching; Fabrication; Heuristic; Instruments; Job shop scheduling; Lot dispatching; machine setup; Machine tools; Manufacturing; Mathematical models; Methodology; Optimization; Packaging; reactive GRASP; Searching; semiconductor assembly and test; Semiconductor device manufacture; Semiconductor device testing; Semiconductors; Studies; Throughput
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/TSM.2010.2041399

The importance of back-end operations in semiconductor manufacturing has been growing steadily in the face of higher customer expectations and stronger competition in the industry. In order to achieve low cycle times, high throughput and high utilization while improving due-date performance, more effective tools are needed to support machine setup and lot dispatching decisions. This paper presents a new model and solution methodology aimed at maximizing the weighted throughput of lots undergoing assembly and test, while ensuring that critical lots are given priority. The problem is formulated as a mixed-integer program and solved with a reactive greedy randomized adaptive search procedure (GRASP). In phase I of the GRASP, machine-tooling combinations are tentatively fixed and lot assignments are made iteratively to arrive at a feasible solution. This process is repeated many times. In phase II, a novel neighborhood search is performed on a subset of good solutions found in phase I. Using a linear programming-Monte Carlo simulation-based algorithm, new machine-tooling combinations are identified within the neighborhood of the solutions carried over, and improvements are sought by optimizing the corresponding lot assignments. The methodology was tested on data provided by a major semiconductor manufacturer. The results show that GRASP achieves high quality solutions comparable to those obtained with CPLEX in often half the time.