A High-Power Broadband Passive Terahertz Frequency Doubler in CMOS

• Published in: IEEE transactions on microwave theory and techniques Vol. 61; no. 3; pp. 1150 - 1160
• Main Authors: Han, R., Afshari, E.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.03.2013; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Broadband; Capacitance; Circuits; CMOS; CMOS integrated circuits; Conversion; conversion efficiency; Design. Technologies. Operation analysis. Testing; Direct current; Electronics; Exact sciences and technology; Filtering; Frequency conversion; frequency doubler; Harmonic analysis; Integrated circuits; Logic gates; Noise levels; passive; ring structure; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; signal source; Structural rings; terahertz; Terahertz frequencies; varactor; Varactors; GHz range; Performance evaluation; Harmonic; Conversion loss; Filtering; Output power; signal source; Input signal; Frequency doubler; Conversion rate; Compact design; Output signal; passive; Ring structure; CMOS; Varactor diode; THz range; High power; Wide band; Complementary MOS technology; terahertz; varactor; Low-power electronics; conversion efficiency
• ISSN: 0018-9480; 1557-9670
• DOI: 10.1109/TMTT.2013.2243465

To realize a high-efficiency terahertz signal source, a varactor-based frequency-doubler topology is proposed. The structure is based on a compact partially coupled ring that simultaneously achieves isolation, matching, and harmonic filtering for both input and output signals at f 0 and 2 f 0 . The optimum varactor pumping/loading conditions for the highest conversion efficiency are also presented analytically along with intuitive circuit representations. Using the proposed circuit, a passive 480-GHz frequency doubler with a measured minimum conversion loss of 14.3 dB and an unsaturated output power of 0.23 mW is reported. Within 20-GHz range, the fluctuation of the measured output power is less than 1.5 dB, and the simulated 3-dB output bandwidth is 70 GHz (14.6%). The doubler is fabricated using 65-nm low-power bulk CMOS technology and consumes near zero dc power.