A Stress-Relaxed Negative Voltage-Level Converter

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 54; no. 3; pp. 282 - 286
• Main Author: Tsiatouhas, Y.E.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2007; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuit simulation; Circuit topology; Circuits; CMOS; CMOS technology; Converters; Delay; Electric potential; Embedded negative voltage-level converter; Energy consumption; level conversion; level shifter; MOS devices; MOS-device voltage stress relaxation; MOSFETs; Power consumption; Power supplies; Simulation; Stress; Voltage

In this brief, a new embedded negative voltage-level converter (level shifter) is presented. The proposed circuit can convert a positive input signal to a negative output signal with reduced or even without (depending on the application) voltage stress on the used MOS devices. The circuit has been d...