A Stress-Relaxed Negative Voltage-Level Converter

In this brief, a new embedded negative voltage-level converter (level shifter) is presented. The proposed circuit can convert a positive input signal to a negative output signal with reduced or even without (depending on the application) voltage stress on the used MOS devices. The circuit has been d...

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Bibliographic Details
Published inIEEE transactions on circuits and systems. II, Express briefs Vol. 54; no. 3; pp. 282 - 286
Main Author Tsiatouhas, Y.E.
Format Journal Article
LanguageEnglish
Published New York IEEE 01.03.2007
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Circuit simulation
Circuit topology
Circuits
CMOS
CMOS technology
Converters
Delay
Electric potential
Embedded negative voltage-level converter
Energy consumption
level conversion
level shifter
MOS devices
MOS-device voltage stress relaxation
MOSFETs
Power consumption
Power supplies
Simulation
Stress
Voltage
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Summary:In this brief, a new embedded negative voltage-level converter (level shifter) is presented. The proposed circuit can convert a positive input signal to a negative output signal with reduced or even without (depending on the application) voltage stress on the used MOS devices. The circuit has been designed in a 0.18-mum triple-well standard CMOS technology, using double-gate-oxide-thickness MOS transistors with an absolute maximum rating of 4.0 V, a nominal power supply of 1.8 V, and a required negative voltage of -3.3 V. Simulation results are provided to demonstrate the efficiency of the proposed topology. According to the results, 1.82-ns delay and 0.53-mW power consumption are reported
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ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2006.886877