10-bit 100-MS/s Pipelined ADC Using Input-Swapped Opamp Sharing and Self-Calibrated V/I Converter

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 19; no. 8; pp. 1438 - 1447
• Main Authors: Kim, Moo-Young, Kim, Jinwoo, Lee, Tagjong, Kim, Chulwoo
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.08.2011; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Amplifiers; Analog-digital conversion; Applied sciences; Circuit properties; CMOS; CMOS process; Converters; Design. Technologies. Operation analysis. Testing; Detectors; Digital-analog conversion; Electric potential; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Error correction; Exact sciences and technology; Frequency measurement; Integrated circuits; Noise levels; Nonlinearity; Opamp-sharing; pipelined analog-to-digital converter (ADC); self-calibration; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors; Signal to noise ratio; switched bias; Switches; Switching converters; Switching, multiplexing, switched capacity circuits; Temperature; V/I converter; Very large scale integration; Voltage; Operational amplifier; switched bias; self-calibration; Temperature sensor; DA converter; Non linear phenomenon; Switching; Pipeline processing; AD converter; Voltage current converter; Selfcalibration; Complementary MOS technology; Electric power consumption; Opamp-sharing; Noise immunity; Selector switch; Error correction; Low-power electronics; Memory effect; pipelined analog-to-digital converter (ADC); Signal to noise and distortion ratio; V/I converter
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2010.2050915

A 31 mW, 10-bit 100-MS/s pipelined analog-to-digital converter (ADC), which alleviates the memory effect occurring in the opamp-sharing technique, and automatically corrects the current error of the V/I converter, has been developed. The proposed ADC achieves low-power consumption, high noise immunity, and has a small area, by employing an input-swapped opamp-sharing technique that switches the summing node in an multiplying digital-to-analog converter and a V/I converter with a process, supply voltage, and temperature condition detector. The ADC shows a differential nonlinearity of less than 0.48 LSB, and an integral nonlinearity of less than 0.95 LSB. Also, an signal-to-noise-and-distortion ratio of 56.2 dB is measured with a 1 MHz input frequency. This has been implemented in a 0.18-μm CMOS process, and occupies 1.6 × 0.8 mm 2 of active area.