A 2.5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 17; no. 12; pp. 1698 - 1708
• Main Authors: JIANG, Shu-Yu, CHENG, Kuo-Hsing, JIAN, Pei-Yi
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.12.2009; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Area measurement; Built-in jitter measurement (BIJM); Circuit design; Circuit properties; Circuits of signal characteristics conditioning (including delay circuits); Clocks; Costs; Counter circuits; Counting circuits; Delay; Delay lines; Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electrical engineering. Electrical power engineering; Electronic circuits; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Exact sciences and technology; Integrated circuits; Jitter; Power electronics, power supplies; Power supplies; Rejection; Sampling; Sampling methods; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; serial-link transceiver; Transceivers; Transmitters; Very large scale integration; Timing jitter; Serial transmission; serial link transceiver; Signal sampling; Gaussian distribution; Receiver; Power supply; Power electronics; Calibration; Clock; Implementation; Transceiver; jitter; Complementary MOS technology; Built-in jitter measurement (BIJM); Delay time; Delay line
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2008.2006476

A 2.5-GHz built-in jitter measurement (BIJM) system is adopted to measure the clock jitter on a transmitter and receiver. The proposed Vernier caliper and autofocus approaches reduce the area cost of delay cells by 48.78% relative to pure Vernier delay line structure with a wide measurement range. The counter circuit occupies an area of 19 mum times 61 mum in the traditional stepping scan approach. The proposed equivalent-signal sampling technique removes the input jitter transfer path from the sampling clock. The power supply rejection design is incorporated into the delay cell and the judge circuit. The layout implementation, calibration, and test time of the proposed BIJM system are all improved. The core circuit occupies an area of only 0.5 mm times 0.15 mm with the 90-nm CMOS process. The Gaussian and uniform distributions jitter is verified at a 5-ps timing resolution and a 2.5-GHz input clock frequency .