A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory

• Published in: IEEE journal of solid-state circuits Vol. 48; no. 10; pp. 2531 - 2540
• Main Authors: Lee, Youngjoo, Yoo, Hoyoung, Jung, Jaehwan, Jo, Jihyuck, Park, In-Cheol
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.10.2013; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Architecture; Buffer storage; CBCH; Circuit properties; Complexity theory; Computer architecture; Decoding; Design. Technologies. Operation analysis. Testing; Digital circuits; ECC; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Energy efficiency; Exact sciences and technology; flash memory; Hardware; Integrated circuits; Integrated circuits by function (including memories and processors); Iterative decoding; low-power architecture; Polynomials; Product introduction; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; Signal convertors; Studies; VLSI; State of the art; Prototype; Updating; Iterative method; Storage access; Implementation; low-power architecture; Coding; Energetic efficiency; Complementary MOS technology; Electric power consumption; Minimum energy; CBCH; NAND circuit; ECC; VLSI; Decoding circuit; Compact design; Decoding; Storage management; Flash memory; Integrated circuit; Error correcting code; Error correction; Low-power electronics; Reliability
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2013.2275655

To improve the reliability of MLC NAND flash memory, this paper presents an energy-efficient high-throughput architecture for decoding concatenated-BCH (CBCH) codes. As the data read from the flash memory is hard-decided in practical applications, the proposed CBCH decoding method is a promising solution to achieve both high error-correction capability and energy efficiency. In the proposed CBCH decoding, the number of on-chip memory accesses consuming much energy is minimized by computing and updating syndromes two-dimensionally. To achieve an area-efficient hardware realization, row and column decoders are unified into one decoder and some syndromes are computed when they are needed. In addition, the decoding throughput is enhanced remarkably by skipping redundant decoding processes. Based on the proposed CBCH decoding architecture, a prototype chip is implemented in a 65-nm CMOS process to decode the (70528, 65536) CBCH code. The proposed decoder provides a decoding throughput of 17.7 Gb/s and an energy efficiency of 2.74 pJ/bit, being vastly superior to the state-of-the-art architectures.