Digital oscillators over finite fields

• Published in: IEEE transactions on signal processing Vol. 48; no. 8; pp. 2406 - 2413
• Main Authors: Chren, W.A., Ridley, J.N.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.08.2000; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Architecture; Arithmetic; Character generation; Circuit properties; CMOS technology; Computation; Computer architecture; Degradation; Delay; Digital; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Finite wordlength effects; Frequency estimation; Galois fields; High speed; Mathematical analysis; Oscillators; Representations; System architecture; Finite field; Digital oscillator; Feedback regulation; Truncation error; Feedback; Oscillator; Complementary MOS technology; Computation error; High speed; Analytical method; Custom circuit; Signal to noise ratio; Sinusoid
• ISSN: 1053-587X; 1941-0476
• DOI: 10.1109/78.852020

This paper shows how the error-free computational property of finite fields can be used to eliminate aperiodicity and SNR degradation problems in digital oscillators. Galois fields are used to eliminate representation and truncation errors in the computation of sinusoid samples. Theorems are presented that characterize those fields that admit all operands necessary for sample generation at a given phase resolution. Two finite field oscillator architectures, exponential feedback, and direct forms are presented, and various design issues associated with operand representation and arithmetic are discussed. It is also shown how field arithmetic can be replaced by arithmetic in the direct product ring associated with a set of specially chosen small fields. This is important in high-speed applications where the loop delay must be minimized. We also present analytical estimates of clocking frequency, latency, and phase and frequency resolution for both architectures. Finally, we present an example ASIC design of a finite ring digital oscillator in 2/spl mu/ CMOS technology.