Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM)

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 19; no. 3; pp. 483 - 493
• Main Authors: Xu, Wei, Sun, Hongbin, Wang, Xiaobin, Chen, Yiran, Zhang, Tong
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.03.2011; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Benchmarks; Cache memories; Cache storage; Computation; Costs; Delay; Design engineering; Design methodology; Design. Technologies. Operation analysis. Testing; Devices; Electronics; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); Magnetic and optical mass memories; Magnetic tunneling; magnetic tunneling junction; Magnetoelectric, magnetostrictive, magnetoacoustic, magnetooptic and magnetothermal devices. Spintronics; Mathematical models; Microprocessors; Random access memory; Read-write memory; Scalability; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; Sizing; spin-torque transfer; Storage and reproduction of information; System performance; Very large scale integration; Performance evaluation; Memory devices; Static random access memory; spin-torque transfer; Scalability; Cache memory; High density; Random access memory; Cache memories; Performance characteristic; Modeling; Switching; Dimensioning; Magnetic tunneling junction; Computer hardware; Non volatile memory; Integrated circuit; Recording density; Electric power consumption; Microprocessor; Cost lowering
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2009.2035509

Because of its high storage density with superior scalability, low integration cost and reasonably high access speed, spin-torque transfer random access memory (STT RAM) appears to have a promising potential to replace SRAM as last-level on-chip cache (e.g., L2 or L3 cache) for microprocessors. Due to unique operational characteristics of its storage device magnetic tunneling junction (MTJ), STT RAM is inherently subject to a write latency versus read latency tradeoff that is determined by the memory cell size. This paper first quantitatively studies how different memory cell sizing may impact the overall computing system performance, and shows that different computing workloads may have conflicting expectations on memory cell sizing. Leveraging MTJ device switching characteristics, we further propose an STT RAM architecture design method that can make STT RAM cache with relatively small memory cell size perform well over a wide spectrum of computing benchmarks. This has been well demonstrated using CACTI-based memory modeling and computing system performance simulations using SimpleScalar. Moreover, we show that this design method can also reduce STT RAM cache energy consumption by up to 30% over a variety of benchmarks.