Robust Level Converter for Sub-Threshold/Super-Threshold Operation:100 mV to 2.5 V

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 19; no. 8; pp. 1429 - 1437
• Main Authors: Ik Joon Chang, Jae-joon Kim, Keejong Kim, Roy, K.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.08.2011; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Chip formation; Circuit properties; Circuits of signal characteristics conditioning (including delay circuits); Clocks; CMOS technology; Converters; Design. Technologies. Operation analysis. Testing; Dynamic range; Electric potential; Electric, optical and optoelectronic circuits; Electrical engineering. Electrical power engineering; Electronic circuits; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Exact sciences and technology; High voltages; Integrated circuits; Level converter; Logic; Logic circuits; Logic design; Low voltage; Power electronics, power supplies; Power supplies; Pulse measurements; Reduction; Robustness; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; subthreshold logic; subthreshold operation; Synchronization; ultra-low voltage operation; Very large scale integration; Dynamic response; Synchronizer; ultra-low voltage operation; Ultralow voltage; Output circuit; Power supply; Logic design; Power electronics; Clock; Synchronization; subthreshold logic; Low voltage; subthreshold operation; High voltage; Level converter; Complementary MOS technology; Converter; Low-power electronics; Threshold logic
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2010.2051240

For ultra low power application, digital sub-threshold logic design has been explored. Extremely low power supply (VDD) of sub-threshold logic results in significant power reduction. However, it is difficult to convert signals from core logic to input/output (I/O) circuits since core VDD is vastly different from high I/O supply voltage. In this work, we propose a level converter based on dynamic logic style for sub-threshold I/O part, having a large dynamic range of conversion. For the level converter, high voltage clock signal needs to be delivered through separate clock path from core logic, leading to clock synchronization problem between high voltage and low voltage clocks. To overcome this issue, we employed a Clock Synchronizer. A test chip is fabricated in 130-nm CMOS technology in order to verify the proposed technique. Hardware measurement results show that the level converter successfully converts 0.3 V 8 MHz pulse to 2.5 V signal.