Improvement of SiO2/4H-SiC Interface properties by post-metallization annealing

• Published in: Microelectronics and reliability Vol. 84; pp. 226 - 229
• Main Authors: Lei, Y.M., Wakabayashi, H., Tsutsui, K., Iwai, H., Furuhashi, M., Tomohisa, S., Yamakawa, S., Kakushima, K.
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 01.05.2018
• ISSN: 0026-2714; 1872-941X
• DOI: 10.1016/j.microrel.2018.03.036

Electrical characteristics of SiC metal-oxide-semiconductor (MOS) capacitors with atomic-layer-deposited SiO2 (ALD-SiO2) gate dielectrics were investigated. Post-metallization annealing (PMA) with W gate electrodes at 950 °C showed a large recovery in the flatband voltage toward the ideal value and the hysteresis was reduced to 36 mV. Interface state density (Dit) of 3 × 1011 cm−2/eV was obtained after the PMA for 5 × 103 s. The concentration of the residual carbon atoms in the SiO2 gate dielectrics has been reduced after annealing, suggesting one of the possible origins of the improvements. •Post-metallization annealing (PMA) improves the interface of SiO2/SiC.•Residual carbon atoms in the atomic layer deposited SiO2 can be reduced.•Hysteresis was reduced to 36 mV.•A low interface state density of 3x1011cm-2/eV was achieved.