Analysis, Modeling and Optimization of Equal Segment Based Approximate Adders

• Published in: IEEE transactions on computers Vol. 68; no. 3; pp. 314 - 330
• Main Authors: Dutt, Sunil, Dash, Satyabrata, Nandi, Sukumar, Trivedi, Gaurav
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accuracy; Adders; Adding circuits; analytical modeling; Analytical models; approximate adders; Approximate computing; Architecture; Configurations; Delay; Delays; Design parameters; Digital systems; equal segment adders; Mathematical models; Model accuracy; Multicore processing; Optimization
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/TC.2018.2871096

Over the past decade, several approximate adders have been proposed in the literature based on the design concept of Equal Segment Adder (ESA). In this approach, an <inline-formula><tex-math notation="LaTeX">N</tex-math> <inline-graphic xlink:href="dutt-ieq1-2871096.gif"/> </inline-formula>-bit adder is segmented into several smaller and independent equally sized accurate sub-adders. An <inline-formula><tex-math notation="LaTeX">N</tex-math> <inline-graphic xlink:href="dutt-ieq2-2871096.gif"/> </inline-formula>-bit ESA has two primary design parameters: (i) Segment size (<inline-formula><tex-math notation="LaTeX">k</tex-math> <inline-graphic xlink:href="dutt-ieq3-2871096.gif"/> </inline-formula>), which represents the maximum length of carry propagation; and (ii) Overlapping bits (<inline-formula><tex-math notation="LaTeX">l</tex-math> <inline-graphic xlink:href="dutt-ieq4-2871096.gif"/> </inline-formula>), which represents the minimum number of bits used in carry prediction, where <inline-formula><tex-math notation="LaTeX">1 \leq k < N</tex-math> <inline-graphic xlink:href="dutt-ieq5-2871096.gif"/> </inline-formula> and <inline-formula><tex-math notation="LaTeX">0 \leq l < k</tex-math> <inline-graphic xlink:href="dutt-ieq6-2871096.gif"/> </inline-formula>. Based on the combinations of <inline-formula><tex-math notation="LaTeX">k</tex-math> <inline-graphic xlink:href="dutt-ieq7-2871096.gif"/> </inline-formula> and <inline-formula><tex-math notation="LaTeX">l</tex-math> <inline-graphic xlink:href="dutt-ieq8-2871096.gif"/> </inline-formula>, an <inline-formula><tex-math notation="LaTeX">N</tex-math> <inline-graphic xlink:href="dutt-ieq9-2871096.gif"/> </inline-formula>-bit ESA has <inline-formula><tex-math notation="LaTeX">N(N-1)/2</tex-math> <inline-graphic xlink:href="dutt-ieq10-2871096.gif"/> </inline-formula> possible configurations. In this paper, we analyse ESAs and propose analytical models to estimate accuracy, delay, power and area of ESAs. The key features of the proposed analytical models are that: (i) They are generalized, i.e., work for all possible configurations of an <inline-formula><tex-math notation="LaTeX">N</tex-math> <inline-graphic xlink:href="dutt-ieq11-2871096.gif"/> </inline-formula>-bit ESA; and (ii) They are superior (i.e., estimate more accurately) or at par to the existing analytical models. From the proposed analytical models, we observe that in an <inline-formula><tex-math notation="LaTeX">N</tex-math> <inline-graphic xlink:href="dutt-ieq12-2871096.gif"/> </inline-formula>-bit ESA, there exist multiple (more than one) configurations which exhibit similar accuracy. However, these configurations exhibit different delay, power and area. Therefore, for a given accuracy, the configurations which provide minimal delay, power and/or area need to be known apriori for efficient, intelligent and goal oriented implementations of ESAs. In this regard, we present an optimization framework that exploits the proposed analytical models to find the optimal configurations of an <inline-formula><tex-math notation="LaTeX">N</tex-math> <inline-graphic xlink:href="dutt-ieq13-2871096.gif"/> </inline-formula>-bit ESA. Further, we know that accuracy of an ESA does not depend on the adder architecture used to implement it, however, its delay, power and area depend significantly. Consequently, the optimal configurations vary with adder architectures used to implement the ESA. In order to cover a wide range of adders, we consider three types of adder architecture in our analysis: (i) Architectures having smaller area (<inline-formula><tex-math notation="LaTeX">O(N)</tex-math> <inline-graphic xlink:href="dutt-ieq14-2871096.gif"/> </inline-formula>); (ii) Architectures having smaller delay (<inline-formula><tex-math notation="LaTeX">O(log_2N)</tex-math> <inline-graphic xlink:href="dutt-ieq15-2871096.gif"/> </inline-formula>); and (iii) Architectures having in-between delay (<inline-formula><tex-math notation="LaTeX">O(N/4)</tex-math> <inline-graphic xlink:href="dutt-ieq16-2871096.gif"/> </inline-formula>) and area (<inline-formula><tex-math notation="LaTeX">O(2N)</tex-math> <inline-graphic xlink:href="dutt-ieq17-2871096.gif"/> </inline-formula>).