A Low-Power SRAM Using Bit-Line Charge-Recycling for Read and Write Operations

• Published in: IEEE journal of solid-state circuits Vol. 45; no. 10; pp. 2173 - 2183
• Main Author: YANG, Byung-Do
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.10.2010; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Bit line; Capacitance; charge-recycling; Chromium; Circuits; Clocks; CMOS; Consumption; Design. Technologies. Operation analysis. Testing; Electric potential; Electronics; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); low power; low swing; Magnetic and optical mass memories; MOSFETs; Power demand; Random access memory; Recycling; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Simulation; SRAM; Static random access memory; Storage and reproduction of information; Voltage; Memory devices; Static random access memory; Bit line; Random access memory; 8 bit Processor; SRAM; charge-recycling; Non volatile memory; Complementary MOS technology; Integrated circuit; Electric power consumption; low power; Recycling; Low-power electronics; low swing; Damaging
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2010.2063950

This paper proposes a low-power SRAM using bit-line charge-recycling for read and write operations. The charge-recycling SRAM (CR-SRAM) reduces the read and write powers by recycling the charge in bit lines. When N bit lines recycle their charges, the swing voltage and power of bit lines are reduced to 1/N and 1/N 2 , respectively. The CR-SRAM utilizes hierarchical bit-line architecture to perform the charge-recycling without static noise margin degradation in memory cells. In the simulation, the CR-SRAM saves 17% read power and 84% write power compared with the conventional SRAM. A CR-SRAM chip with 4 K × 8 bits is implemented in a 0.13-μm CMOS process. It consumes 0.128-mW read power and 0.135-mW write power at f CLK = 100 MHz and V DD = 1.2 V.