OLED Microdisplay With Monolithically Integrated CAAC-OS FET and Si CMOS Achieved by Two-Dimensionally Arranged Silicon Display Drivers

• Published in: IEEE journal of the Electron Devices Society Vol. 12; pp. 187 - 194
• Main Authors: Kozuma, Munehiro, Komura, Yusuke, Miyata, Shoki, Okamoto, Yuki, Tamatsukuri, Yuki, Inoue, Hiroki, Saito, Toshihiko, Kobayashi, Hidetomo, Onuki, Tatsuya, Yanagisawa, Yuichi, Takeuchi, Toshihiko, Okazaki, Yutaka, Kunitake, Hitoshi, Nakamura, Daiki, Nagata, Takaaki, Yamane, Yasumasa, Ikeda, Makoto, Yamazaki, Shunpei
• Format: Journal Article
• Language: English
• Published: New York IEEE 2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: and foveated rendering; CAAC-OS; CMOS; Display devices; driver; Driver stages; Field effect transistors; high frame rate; Logic gates; microdisplay; Microdisplays; Organic light emitting diodes; Pixels; Power consumption; Power demand; Reduction; Si CMOS; Silicon; Timing
• ISSN: 2168-6734; 2168-6734
• DOI: 10.1109/JEDS.2024.3366938

We developed an organic light-emitting diode (OLED)/oxide semiconductor (OS)/silicon (Si) display in which Si CMOS display drivers can be arranged two-dimensionally by monolithically stacking <inline-formula> <tex-math notation="LaTeX">{c} </tex-math></inline-formula>-axis-aligned crystalline oxide semiconductor (CAAC-OS) FETs over Si CMOS. A CAAC-OS FET exhibits a higher withstand voltage than a SiFET of the same size, enabling considerable pixel area reduction. The CAAC-OS FET can be driven even at a low refresh rate owing to its extremely low off-state current, making it an ideal choice for constructing pixel circuits. This integration of CAAC-OS FETs empowers our display system to offer enhanced resolution and reduced power consumption. The two-dimensionally arranged drivers have two features. (1) Si drivers can be arranged in two-dimensional driver blocks with a desired size, which provides flexibility to increase the number of driver stages and adjust resolution and frame rates for each driver block via logic processing. (2) The circuit performance of the system can be changed to prioritize frame rate and power consumption, which have a trade-off relation, of the driver by providing a redundant circuit in the driver. To demonstrate these features, we fabricated a prototype display and confirmed that our driver had a power consumption of 1,094.96 mW at 30 Gbps in a normal mode and 524.55 mW at 3.75 Gbps in a foveated rendering (FR) mode, revealing a 52% reduction in power consumption in the FR mode. This technology is expected to achieve high-frame-rate performance, which has been difficult to achieve in conventional microdisplays.