A Distributed Oscillator Based All-Digital PLL With a 32-Phase Embedded Phase-to-Digital Converter

• Published in: IEEE journal of solid-state circuits Vol. 46; no. 11; pp. 2650 - 2660
• Main Authors: Takinami, K., Strandberg, R., Liang, P. C. P., Le Grand de Mercey, G., Wong, T., Hassibi, M.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.11.2011; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: all-digital phase-locked loop; Analog to digital converters; Applied sciences; Circuit properties; Circuits; Circuits of signal characteristics conditioning (including delay circuits); Clocks; CMOS; Converters; Delay; Digital; digitally-controlled oscillator; Distributed oscillator; Electric, optical and optoelectronic circuits; Electronic circuits; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Exact sciences and technology; Inverters; low phase noise; Noise; Oscillators; Oscillators, resonators, synthetizers; Phase locked loops; Phase noise; phase-to-digital converter; rotary traveling wave; Signal convertors; time-to-digital converter; Phase noise; Inverter; digitally-controlled oscillator; Low noise circuit; Distributed oscillator; Digital converter; Numerical method; low phase noise; Travelling wave; Phase locked loop; Digital control; all-digital phase-locked loop; time-to-digital converter; Oscillator; Complementary MOS technology; Time to digital conversion; phase-to-digital converter; Digital circuit; rotary traveling wave; Time converter; Delay time
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2011.2164011

This paper presents a wide-bandwidth, low-noise 4 GHz All-Digital PLL. It uses a rotary traveling wave oscillator (RTWO) as the oscillator core. By using multiphase signals available from the RTWO, the analog phase information is directly converted into the digital domain. Unlike the conventional time-to-digital converter (TDC) approach, it eliminates power hungry inverter delay chains as well as real time period normalization. The proposed approach significantly simplifies the ADPLL architecture while maintaining excellent phase noise. The PLL is implemented in a 65 nm CMOS process. The 32-phase embedded phase-to-digital converter (PDC) achieves 2π/64 phase resolution. The measured in-band phase noise is -108 dBc/Hz at 4 GHz with a 78 MHz reference and a 1 MHz loop bandwidth.