A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC

• Published in: IEEE journal of solid-state circuits Vol. 45; no. 11; pp. 2217 - 2226
• Main Authors: Chung, Yung-Hui, Wu, Jieh-Tsorng
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.11.2010; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accuracy; Amplification; Amplifiers; Analog-digital conversion; Applied sciences; Calibration; Capacitors; Circuit properties; Circuits; Clocks; CMOS; CMOS integrated circuits; Comparators; comparators (circuits); Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Gain; Integrated circuits; Latches; Noise levels; Residues; Resistors; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors; subranging ADC; two-step ADC; Spurious free dynamic range; Calibration; Amplifier; Analog-digital conversion; Sequential circuit; AD converter; Complementary MOS technology; subranging ADC; Latch circuit; two-step ADC; Open loop; Electric power consumption; Comparator circuit; Gain; comparators (circuits); Signal to noise ratio
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2010.2063590

A 10-bit 100-MS/s two-step ADC was fabricated using a 90 nm CMOS technology. To reduce power consumption, the ADC uses latch-type comparators for signal digitalization and an open-loop amplifier for residue amplification. The accuracy of the comparators is improved by offset calibration. The gain accuracy and the linearity of the residue amplifier are enhanced by digital background calibration. The ADC consumes 6 mW from a 1 V supply. Measured SNR and SFDR are 58.2 dB and 75 dB respectively. Measured ENOB is 9.34 bits. The FOM is 100 fJ·V per conversion-step.