Sequential Element Design With Built-In Soft Error Resilience

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 14; no. 12; pp. 1368 - 1378
• Main Authors: Ming Zhang, Mitra, S., Mak, T.M., Seifert, N., Wang, N.J., Quan Shi, Kee Sup Kim, Shanbhag, N.R., Patel, S.J.
• Format: Journal Article
• Language: English
• Published: Piscataway, NJ IEEE 01.12.2006; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Circuit faults; Circuit properties; Circuit simulation; Coupling circuits; Design engineering; Design. Technologies. Operation analysis. Testing; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Error analysis; Error correction; Error correction & detection; Exact sciences and technology; fault injection; Flip-flops; Integrated circuits; Latches; Microprocessors; Resilience; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; sequential element design; soft error rate (SER); Soft errors; Studies; Testing, measurement, noise and reliability; Theoretical study. Circuits analysis and design; Tunable circuits and devices; Very large scale integration; Tunable circuit; Circuit simulation; Fault simulation; Bit error rate; Debugging; Reuse; soft error rate (SER); Integrated circuit design; Design for testability; Bistable; sequential element design; Soft error; Integrated circuit; Radiation effect; Error detection; Error correcting code; Error correction; Microprocessor; fault injection; Reliability
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2006.887832

This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced soft errors in latches and flip-flops. The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design-for-testability and design-for-debug resources to minimize area overheads. Circuit simulations using a sub-90-nm technology show that the presented designs achieve more than a 20-fold reduction in cell-level soft error rate (SER). Fault injection experiments conducted on a microprocessor model further demonstrate that chip-level SER improvement is tunable by selective placement of the presented error-correcting designs. When coupled with error correction code to protect in-pipeline memories, the BISER flip-flop design improves chip-level SER by 10 times over an unprotected pipeline with the flip-flops contributing an extra 7-10.5% in power. When only soft errors in flips-flops are considered, the BISER technique improves chip-level SER by 10 times with an increased power of 10.3%. The error correction mechanism is configurable (i.e., can be turned on or off) which enables the use of the presented techniques for designs that can target multiple applications with a wide range of reliability requirements