Timing Optimization and Noise Tolerance for Dynamic CMOS Susceptible to Process Variations

• Published in: IEEE transactions on semiconductor manufacturing Vol. 25; no. 2; pp. 255 - 265
• Main Authors: Yelamarthi, K., Chen, Chien-In Henry
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.05.2012; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Circuits; CMOS; CMOS circuit; CMOS integrated circuits; Competition; Delay; delay uncertainty; Design engineering; Design. Technologies. Operation analysis. Testing; Dynamical systems; Dynamics; Electronics; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); Logic gates; Noise; Noise tolerance; Optimization; process variations; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Time measurements; timing optimization; Transistors; Performance evaluation; MOS technology; High performance; MOSFET; VLSI circuit; CMOS circuit; Worst case method; Dynamic circuit; Algorithm; timing optimization; Implementation; Optimization; Dimensioning; Energy dissipation; Complementary MOS technology; delay uncertainty; process variations; Integrated circuit; Noise immunity; Delay time; CMOS integrated circuits; Microprocessor; noise tolerance

Dynamic CMOS circuits are significantly used in high-performance very large-scale integrated (VLSI) systems. However, they suffer from limitations such as noise tolerance, charge leakage, and power consumption. With the escalating impact of process variations on design performance, aggressive techno...