Timing Optimization and Noise Tolerance for Dynamic CMOS Susceptible to Process Variations

• Published in: IEEE transactions on semiconductor manufacturing Vol. 25; no. 2; pp. 255 - 265
• Main Authors: Yelamarthi, K., Chen, Chien-In Henry
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.05.2012; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Circuits; CMOS; CMOS circuit; CMOS integrated circuits; Competition; Delay; delay uncertainty; Design engineering; Design. Technologies. Operation analysis. Testing; Dynamical systems; Dynamics; Electronics; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); Logic gates; Noise; Noise tolerance; Optimization; process variations; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Time measurements; timing optimization; Transistors; Performance evaluation; MOS technology; High performance; MOSFET; VLSI circuit; CMOS circuit; Worst case method; Dynamic circuit; Algorithm; timing optimization; Implementation; Optimization; Dimensioning; Energy dissipation; Complementary MOS technology; delay uncertainty; process variations; Integrated circuit; Noise immunity; Delay time; CMOS integrated circuits; Microprocessor; noise tolerance
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/TSM.2012.2185961

Dynamic CMOS circuits are significantly used in high-performance very large-scale integrated (VLSI) systems. However, they suffer from limitations such as noise tolerance, charge leakage, and power consumption. With the escalating impact of process variations on design performance, aggressive technology scaling, noise in dynamic CMOS circuit has become an imperative design challenge. The design performance of dynamic circuits has to be first improved for reliable operation of VLSI systems. Alongside, this impact of process variation is worse in circuits with multiple timing paths such as those used in microprocessors. In this paper, these problems of process variations, timing, noise tolerance, and power are investigated together for performance optimization. We propose a process variation-aware load-balance of multiple paths transistor sizing algorithm to: 1) improve worst-case delay, delay uncertainty, and sensitivity due to process variations in dynamic CMOS circuits, and 2) optimize dynamic CMOS circuits with MOSFET-based keepers to improve the noise tolerance. Implemented using 90-nm CMOS process, the proposed algorithm has demonstrated an average improvement in worst-case delay by 34%, delay uncertainty by 40.3%, delay sensitivity by 25.1%, and noise margins by 19.4% when compared to their initial performances.