System-level power-performance tradeoffs for reconfigurable computing

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 14; no. 7; pp. 730 - 739
• Main Authors: Noguera, J., Badia, R.M.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: Piscataway, NJ IEEE 01.07.2006; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Application software; Applied sciences; Architecture; Computation; Computer architecture; Devices; Electric, optical and optoelectronic circuits; Electronics; Embedded computing; Embedded system; Energy consumption; Exact sciences and technology; Hardware; Hardware/software (HW/SW) codesign; Methodology; Partitioning; power-performance tradeoffs; Programmable logic arrays; Reconfigurable architectures; reconfigurable computing (RC); Reconfigurable logic; System-on-a-chip; Theoretical study. Circuits analysis and design; Very large scale integration; Performance evaluation; Mobile radiocommunication; Mobile phone; Hardware/software (HW/SW) codesign; Circuit design; Codesign; Algorithm; Case study; Partitioning; reconfigurable computing (RC); Integrated circuit; power- performance tradeoffs; Software; Reconfigurable architectures; Low-power electronics; Custom circuit
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2006.878343

In this paper, we propose a configuration-aware data-partitioning approach for reconfigurable computing. We show how the reconfiguration overhead impacts the data-partitioning process. Moreover, we explore the system-level power-performance tradeoffs available when implementing streaming embedded applications on fine-grained reconfigurable architectures. For a certain group of streaming applications, we show that an efficient hardware/software partitioning algorithm is required when targeting low power. However, if the application objective is performance, then we propose the use of dynamically reconfigurable architectures. We propose a design methodology that adapts the architecture and algorithms to the application requirements. The methodology has been proven to work on a real research platform based on Xilinx devices. Finally, we have applied our methodology and algorithms to the case study of image sharpening, which is required nowadays in digital cameras and mobile phones