Enhanced Total Ionizing Dose Hardness of Deep Sub-Micron Partially Depleted Silicon-on-Insulator n-Type Metal-Oxide-Semiconductor Field Effect Transistors by Applying Larger Back-Gate Voltage Stress

The larger back-gate voltage stress is applied on 130nm partially depleted silicon-on-insulator n-type metal-oxide-semiconductor field-effect transistors isolated by shallow trench isolation. The experimental results show that the back-gate sub-threshold hump of the device is eliminated by stress. T...

Full description

Saved in:
Bibliographic Details
Published inChinese physics letters Vol. 31; no. 12; pp. 126101 - 1-126101-3
Main Authors Zheng, Qi-Wen, Cui, Jiang-Wei, Yu, Xue-Feng, Guo, Qi, Zhou, Hang, Ren, Di-Yuan
Format Journal Article
LanguageEnglish
Published 01.12.2014
Subjects
Depletion
Devices
Electric potential
Field effect transistors
Hardness
Semiconductor devices
Stresses
Voltage
Online AccessGet full text

Cover

More Information
Summary:The larger back-gate voltage stress is applied on 130nm partially depleted silicon-on-insulator n-type metal-oxide-semiconductor field-effect transistors isolated by shallow trench isolation. The experimental results show that the back-gate sub-threshold hump of the device is eliminated by stress. This observed behavior is caused by the high electric field in the oxide near the bottom corner of the silicon island. The total ionizing dose hardness of devices with pre back-gate stress is enhanced by the interface states induced by stress.
Bibliography:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
ISSN:0256-307X
1741-3540
DOI:10.1088/0256-307X/31/12/126101