A 440-nA True Random Number Generator for Passive RFID Tags

This paper describes a 440-nA true random number (RN) generator for passive ultrahigh frequency radio frequency identification (RFID) tags that operate in the 900-MHz band. Since passive tags derive their power supply through the rectification of the incoming RF signal, limited power is available, a...

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Bibliographic Details
Published inIEEE transactions on circuits and systems. I, Regular papers Vol. 55; no. 11; pp. 3723 - 3732
Main Authors Balachandran, G.K., Barnett, R.E.
Format Journal Article
LanguageEnglish
Published New York IEEE 01.12.2008
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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ISSN1549-8328
1558-0806
DOI10.1109/TCSI.2008.927220

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Summary:This paper describes a 440-nA true random number (RN) generator for passive ultrahigh frequency radio frequency identification (RFID) tags that operate in the 900-MHz band. Since passive tags derive their power supply through the rectification of the incoming RF signal, limited power is available, and hence, a typical total IC current budget is less than a few microamperes. An RN is generated by a passive RFID tag on the fly, and it is used by the reader to identify the tag uniquely and communicate with it in a field consisting of many tags. The RN in this paper consists of a 16-bit-long deterministic binary sequence to which a 3-bit true RN is added. Without the 3-bit true RN, if two tags happen to have the same deterministic 16-bit sequence, a collision occurs, and there is no way to resolve it. In this paper, we propose a power efficient way of generating the 3-bit true RN using the jitter-sampled carrier technique. This technique subsamples the already present 900-MHz RF carrier using a jittered (noisy) clock. The design challenges of sampling a high-frequency signal that swings above and below ground are described. In addition, the generation of a jitter of adequate magnitude with adequate high-frequency spectral content to ensure that the number is truly random is also described. Measurement results on a silicon prototype implemented in a 130-nm analog CMOS process are provided.
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ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2008.927220