Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 54; no. 5; pp. 933 - 940
• Main Authors: Cannizzaro, S.O., Grasso, A.D., Mita, R., Palumbo, G., Pennisi, S.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2007; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog computers; Circuit testing; Circuit topology; Circuits; CMOS; Compensation; Design automation; Design engineering; Drives; Frequency; Integrated circuit technology; Integrated circuit yield; Knowledge base; multistage amplifiers; nested-Miller compensation; Operational amplifiers; operational transconductance amplifiers (OTAs); Prototypes; Specifications; Transconductance
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2007.895520

Design procedures for three-stage CMOS operational transconductance amplifiers employing nested-Miller frequency compensation are presented in this paper. After describing the basic methodology on a Class-A topology, some modifications, to increase swing, slew-rate and current drive capability, are subsequently discussed for a Class-AB solution. The approaches developed are simple as they do not introduce unnecessary circuit constraints and yield accurate results. They are hence suited for a pencil-and-paper design, but can be easily integrated into an analog knowledge-based computer-aided design tool. Experimental prototypes, designed in a 0.35-mum technology by following the proposed procedures, were fabricated and tested. Measurement results were found in close agreement with the target specifications