Transactional Memory: An Overview

• Published in: IEEE MICRO Vol. 27; no. 3; pp. 8 - 29
• Main Authors: Harris, T., Cristal, A., Unsal, O.S., Ayguade, E., Gagliardi, F., Smith, B., Valero, M.
• Format: Journal Article Publication
• Language: English
• Published: Los Alamitos IEEE 01.05.2007; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Arquitectura de computadors; Arquitectures paral·leles; Chips; Computation; Computer errors; Computer memory; Concurrent computing; Distributed shared memory systems; Emmagatzematge i recuperació de la informació; Gestió de memòria (Informàtica); Informàtica; memory architecture; Memory management (Computer science); Microprocessors; Multicore processing; Multiprocessing; Multiprocessor; multithreading; Parallel processing; Parallel programming; Parallel programming (Computer science); Programació en paral·lel (Informàtica); Programmers; Programming profession; Protection; Scalability; Semiconductors; Sistemes d'informació; Storage management; Supercomputers; Tasks; transactional memory; Writing; Àrees temàtiques de la UPC
• ISSN: 0272-1732; 1937-4143
• DOI: 10.1109/MM.2007.63

Writing applications that benefit from the massive computational power of future multicore chip multiprocessors will not be an easy task for mainstream programmers accustomed to sequential algorithms rather than parallel ones. This article presents a survey of transactional memory, a mechanism that promises to enable scalable performance while freeing programmers from some of the burden of modifying their parallel code.