A Three-Dimensional Stacked-Chip Star-Wiring Interconnection for a Digital Noise-Free and Low-Jitter I/O Clock Distribution Network

• Published in: IEEE microwave and wireless components letters Vol. 16; no. 12; pp. 651 - 653
• Main Authors: RYU, Chunghyun, CHUNG, Daehyun, LEE, Choonheung, KIM, Jinhan, BAE, Kicheol, YU, Jiheon, LEE, Seungjae, KIM, Joungho
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.12.2006; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Circuit noise; Clocks; Design. Technologies. Operation analysis. Testing; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Exact sciences and technology; Integrated circuit interconnections; Integrated circuits; Interconnection; Jitter; Low-jitter clock; low-skew clock; Network-on-a-chip; Networks; Noise; noise coupling; Noise generators; Packaging; Power generation; Power supplies; power supply noise; repeater; Repeaters; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Switching theory; three-dimensional (3-D) stacked-chip star-wiring clock distribution; Timing jitter; Die; Lossless circuit; Low noise circuit; Low-jitter clock; Power supply; noise coupling; Background noise; Clock; low-skew clock; Noise level; Wiring; three-dimensional (3-D) stacked-chip star-wiring clock distribution; Three dimensional model; Asymmetry; Interconnection; power supply noise; Electronic packaging; Integrated circuit; Switching power supply; Repeater; Delay time; Distribution network; Cascade connection
• ISSN: 1531-1309; 1558-1764
• DOI: 10.1109/LMWC.2006.885604

Cascaded repeaters are indispensable circuit elements in conventional on-chip clock distribution networks due to heavy loss characteristics of on-chip global interconnections. However, cascaded repeaters cause significant jitter and skew problems in clock distribution networks when they are affected by power supply switching noise generated by digital logic blocks located on the same die. In this letter, we present a new three-dimensional (3-D) stacked-chip star-wiring interconnection scheme to make a clock distribution network free from both on-chip and package-level power supply noise coupling. The proposed clock distribution scheme provides an extremely low-jitter and low-skew clock signal by replacing the cascaded repeaters with lossless star-wiring interconnections on a 3-D stacked-chip package. We have demonstrated a 500-MHz input/output (I/O) clock delivery with 34-ps peak-to-peak jitter and a skew of 11ps, while a conventional I/O clock scheme exhibited a 146-ps peak-to-peak jitter and a 177-ps skew in the same power supply noise environment