APA (7th ed.) Citation

Wang, K., Ran, Y., Jiang, H., & Marek-Sadowska, M. (2005). General skew constrained clock network sizing based on sequential linear programming. IEEE transactions on computer-aided design of integrated circuits and systems, 24(5), 773-782. https://doi.org/10.1109/TCAD.2005.846362

Chicago Style (17th ed.) Citation

Wang, Kai, Y. Ran, Hailin Jiang, and M. Marek-Sadowska. "General Skew Constrained Clock Network Sizing Based on Sequential Linear Programming." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems 24, no. 5 (2005): 773-782. https://doi.org/10.1109/TCAD.2005.846362.

MLA (9th ed.) Citation

Wang, Kai, et al. "General Skew Constrained Clock Network Sizing Based on Sequential Linear Programming." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 24, no. 5, 2005, pp. 773-782, https://doi.org/10.1109/TCAD.2005.846362.