General skew constrained clock network sizing based on sequential linear programming

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 24; no. 5; pp. 773 - 782
• Main Authors: Kai Wang, Ran, Y., Hailin Jiang, Marek-Sadowska, M.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2005; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accuracy; Analytical models; Clock slew; Clocks; Delay effects; Integrated circuit interconnections; Linear programming; Power supplies; power supply noise; Scheduling; sequential linear programming; System performance; Wire
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2005.846362

We investigate the problem of clock network sizing subject to general skew constraints. A novel approach based on sequential linear programming is presented. The original nonlinear programming problem is transformed into a sequence of linear programs by taking the first-order Taylor's expansion of clock path delay with respect to buffer and/or wire widths. For each linear program, the sensitivities of clock path delay, with respect to buffer and/or wire widths, are efficiently updated by applying time-domain analysis to the clock network in a divide-and-conquer fashion. Our technique can take into account power supply and process variations. We demonstrate experimentally that the proposed technique is not only capable of optimizing effectively the skew and area of clock network, but also of providing more accurate delay and skew results compared to the traditional approaches.