Independent Double-Gate Fin SONOS Flash Memory Fabricated With Sidewall Spacer Patterning

• Published in: IEEE transactions on electron devices Vol. 56; no. 8; pp. 1721 - 1728
• Main Authors: Yun, Jang-Gn, Kim, Yoon, Park, Il Han, Lee, Jung Hoon, Kang, Daewoong, Lee, Myoungrack, Shin, Hyungcheol, Lee, Jong Duk, Park, Byung-Gook
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.08.2009; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Compound structure devices; Design. Technologies. Operation analysis. Testing; Devices; Electrical properties; Electronics; Exact sciences and technology; Fabrication; Fin silicon-oxide-nitride-oxide-semiconductor (SONOS) Flash memory; Flash memory; Flash memory (computers); Gates; Integrated circuits; Integrated circuits by function (including memories and processors); interference coupling; Lithography; Logic gates; Microelectronic fabrication (materials and surfaces technology); paired cell interference (PCI); Patterning; Photolithography; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; separated double gates; sidewall spacer patterning; Silicon; SONOS devices; Spacers; Threshold voltage; SONOS structure; Fin silicon-oxide-nitride-oxide-semiconductor (SONOS) Flash memory; sidewall spacer patterning; Microelectronic fabrication; Flash memory; Non volatile memory; Manufacturing process; paired cell interference (PCI); Spacer; Integrated circuit; interference coupling; separated double gates; Photolithography; Semiconductor storage; Electrical characteristic
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2009.2024228

Fin silicon-oxide-nitride-oxide-semiconductor (SONOS) flash memories having independent double gates are fabricated and characterized. This device has two sidewall gates sharing one Si fin. To achieve narrow Si fin width over the photolithography limitation, sidewall spacer patterning is adopted. Specific fabrication processes for the fin SONOS flash memory having independent double gates are described. Electrical properties related to the opposite gate dependence are characterized. Measurement results of the paired cell interference are delivered.