An Area- and Energy-Efficient Spiking Neural Network with Spike-Time-Dependent Plasticity Realized with SRAM Processing-in-memory Macro and On-chip Unsupervised Learning

• Published in: IEEE transactions on biomedical circuits and systems Vol. 17; no. 1; pp. 1 - 12
• Main Authors: Liu, S., Wang, J. J., Zhou, J. T., Hu, S. G., Yu, Q., Chen, T. P., Liu, Y.
• Format: Journal Article
• Language: English
• Published: United States IEEE 01.02.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Biological neural networks; Capacitors; Co-design; Energy efficiency; Firing pattern; Hardware; Learning; Machine learning; Membrane potential; MNIST; Models, Neurological; Neural networks; Neural Networks, Computer; Neural plasticity; Neuronal Plasticity - physiology; on-chip unsupervised learning; Plastic properties; Plasticity; Power consumption; processing-in-memory (PIM); Random access memory; spike-time-dependent plasticity (STDP); Spiking; Spiking neural network (SNN); SRAM; Static random access memory; Supervised learning; System-on-chip; Time dependence; Unsupervised learning; Unsupervised Machine Learning
• ISSN: 1932-4545; 1940-9990
• DOI: 10.1109/TBCAS.2023.3242413

In this article, we present a spiking neural network (SNN) based on both SRAM processing-in-memory (PIM) macro and on-chip unsupervised learning with Spike-Time-Dependent Plasticity (STDP). Co-design of algorithm and hardware for hardware-friendly SNN and efficient STDP-based learning methodology is used to improve area and energy efficiency. The proposed macro utilizes charge sharing of capacitors to perform fully parallel Reconfigurable Multi-bit PIM Multiply-Accumulate (RMPMA) operations. A thermometer-coded Programmable High-precision PIM Threshold Generator (PHPTG) is designed to achieve low differential non-linearity (DNL) and high linearity. In the macro, each column of PIM cells and a comparator act as a neuron to accumulate membrane potential and fire spikes. A simplified Winner Takes All (WTA) mechanism is used in the proposed hardware-friendly architecture. By combining the hardware-friendly STDP algorithm as well as the parallel Word Lines (WLs) and Processing Bit Lines (PBLs), we realize unsupervised learning and recognize the Modified National Institute of Standards and Technology (MNIST) dataset. The chip for the hardware implementation was fabricated with a 55nm CMOS process. The measurement shows that the chip achieves a learning efficiency of 0.47 nJ/pixel, with a learning energy efficiency of 70.38 TOPS/W. This work paves a pathway for the on-chip learning algorithm in PIM with lower power consumption and fewer hardware resources.