Independent-Double-Gate FinFET SRAM for Leakage Current Reduction

• Published in: IEEE electron device letters Vol. 30; no. 7; pp. 757 - 759
• Main Authors: Endo, K., O'uchi, S.-I., Ishikawa, Y., Liu, Y., Matsukawa, T., Sakamoto, K., Masahara, M., Tsukada, J., Ishii, K., Yamauchi, H., Suzuki, E.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.07.2009; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Controllability; Design. Technologies. Operation analysis. Testing; Electrodes; Electronics; Energy consumption; Etching; Exact sciences and technology; Fin-type MOSFET (FinFET); FinFETs; Gates; independent double gate (IDG); Integrated circuits; Integrated circuits by function (including memories and processors); Leakage current; MOSFET circuits; MOSFETs; Nanoelectronics; Power consumption; Random access memory; Reduction; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; SRAM; Static random access memory; Tin; Transistors; Voltage control; Static random access memory; MOSFET; Random access memory; Dual gate transistor; SRAM; Self aligned technology; Engraving; Power consumption; Integrated circuit; Separation process; Fin-type MOSFET (FinFET); Controllability; Leakage current; independent double gate (IDG)
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2009.2021075

An independent-double-gate (IDG) fin-type MOSFET (FinFET) SRAM has been successfully fabricated with considerable leakage current reduction. The new SRAM consists of IDG-FinFETs which have flexible V th controllability. The IDG-FinFET with a TiN metal gate is fabricated by a newly developed gate-separation etching process. By appropriately controlling the V th of the IDG-FinFET, we have successfully demonstrated the reduction of the leakage current and power consumption of the SRAM circuitry.