A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration

• Published in: IEEE journal of solid-state circuits Vol. 41; no. 11; pp. 2417 - 2423
• Main Authors: Daito, M., Matsui, H., Ueda, M., Iizuka, K.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.11.2006; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog-digital conversion; Analog-to-digital converter (ADC); Applied sciences; Calibration; Capacitors; Circuit properties; Circuits; CMOS; CMOS analog integrated circuits; Consumption; Design. Technologies. Operation analysis. Testing; Digital; Distortion; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Feedback; Gain; Integrated circuits; Noise levels; Nonlinear distortion; Operational amplifiers; Prototypes; Sampling methods; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors; Transfer functions; Voltage; Third harmonic; Prototype; CMOS analog integrated circuits; Third order; Analog-to-digital converter (ADC); Spurious free dynamic range; DA converter; Pipeline processing; Harmonics suppression; AD converter; Complementary MOS technology; CMOS analogue integrated circuits; calibration; Gain; Signal to noise and distortion ratio; distortion
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2006.882886

A new digital distortion calibration technique is demonstrated in a 14-bit 20-MS/s pipelined analog-to-digital converter (ADC). Calibration parameters are obtained in a way similar to conventional digital gain calibration. The prototype ADC has been fabricated in a 0.18-mum CMOS process and consumes 33.7 mW at 2.8 V. Using the proposed calibration method, a 15-dB improvement of the third-order harmonic rejection is achieved. The measured SNDR and SFDR are 71.6 and 82.3 dB, respectively