A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology

• Published in: IEEE journal of solid-state circuits Vol. 41; no. 12; pp. 2885 - 2900
• Main Authors: Bulzacchelli, J.F., Meghelli, M., Rylov, S.V., Rhee, W., Rylyakov, A.V., Ainspan, H.A., Parker, B.D., Beakes, M.P., Aichin Chung, Beukema, T.J., Pepeljugoski, P.K., Shan, L., Kwark, Y.H., Gowda, S., Friedman, D.J.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.12.2006; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adaptive equalizer; Applied sciences; Channels; Circuit properties; Circuits of signal characteristics conditioning (including delay circuits); CMOS; CMOS technology; Decision feedback equalizers; decision-feedback equalizer; Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Equalizers; Exact sciences and technology; feed-forward equalizer; Feedback; Feedback loop; Feedforward systems; Integrated circuits; Jitter; Optical signal processing; Oscillators, resonators, synthetizers; Phase locked loops; Propagation losses; Receivers; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; serial link; Studies; transceiver; Transceivers; Transmitters; Performance evaluation; Timing jitter; Serial transmission; Voltage controlled oscillator; Feedback regulation; Receiver; Decision feedback equalizers; Output signal; serial link; Phase locked loop; Transceiver; Complementary MOS technology; decision-feedback equalizer; feed-forward equalizer; Adaptive equalizer
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2006.884342

This paper presents a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications. To mitigate the effects of channel loss and other impairments, a 5-tap decision feedback equalizer (DFE) is included in the receiver and a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter. This combination of DFE and FFE permits error-free NRZ signaling over channels with losses exceeding 30 dB. Low jitter clocks for the transmitter and receiver are supplied by a PLL with LC VCO. Operation at 10-Gb/s with good power efficiency is achieved by using half-rate architectures in both transmitter and receiver. With the transmitter producing an output signal of 1200mVppd, one transmitter/receiver pair and one PLL consume 300mW. Design enhancements of a half-rate DFE employing one tap of speculative feedback and four taps of dynamic feedback allow its loop timing requirements to be met. Serial link experiments with a variety of test channels demonstrate the effectiveness of the FFE/DFE equalization