Optimizing Inverse-Mode SiGe HBTs for Immunity to Heavy-Ion-Induced Single-Event Upset
Inverse-mode (collector-up) operation is proposed as a solution to the single-event-upset susceptibility observed in commercially available bulk silicon-germanium heterojunction bipolar transistors. Inverse-mode performance optimization techniques, which require no process changes or added lithograp...
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Published in | IEEE electron device letters Vol. 30; no. 5; pp. 511 - 513 |
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Main Authors | , , |
Format | Journal Article |
Language | English |
Published |
New York, NY
IEEE
01.05.2009
Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
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Summary: | Inverse-mode (collector-up) operation is proposed as a solution to the single-event-upset susceptibility observed in commercially available bulk silicon-germanium heterojunction bipolar transistors. Inverse-mode performance optimization techniques, which require no process changes or added lithographic masks, are demonstrated, yielding inverse-mode transistor performance capable of supporting gigabit-per-second digital logic needed in space-based communication systems. |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 0741-3106 1558-0563 |
DOI: | 10.1109/LED.2009.2016678 |